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REVIEWED: SIMD intrinsics checks and usage
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Ray
192
src/external/rlsw.h
vendored
192
src/external/rlsw.h
vendored
@ -40,6 +40,14 @@
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* If not defined, the library is in header only mode and can be included in other headers
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* or source files without problems. But only ONE file should hold the implementation
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*
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* #define RLSW_USE_SIMD_INTRINSICS
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* Detect and use SIMD intrinsics on the host compilation platform
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* SIMD could improve rendering considerable vectorizing some raster operations
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* but the target platforms running the compiled program with SIMD enabled
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* must support the SIMD the program has been built for, making them only
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* recommended under specific situations and only if the developers know
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* what are they doing; this flag is not defined by default
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*
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* rlsw capabilities could be customized just defining some internal
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* values before library inclusion (default values listed):
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*
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@ -636,59 +644,58 @@ SWAPI void swBindTexture(uint32_t id);
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#define SW_ARCH_RISCV
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#endif
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// Check for SIMD vector instructions
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#if defined(__FMA__) && defined(__AVX2__)
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#define SW_HAS_FMA_AVX2
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#include <immintrin.h>
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#endif
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#if defined(__FMA__) && defined(__AVX__)
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#define SW_HAS_FMA_AVX
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#include <immintrin.h>
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#endif
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#if defined(__AVX2__)
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#define SW_HAS_AVX2
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#include <immintrin.h>
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#endif
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#if defined(__AVX__)
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#define SW_HAS_AVX
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#include <immintrin.h>
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#endif
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#if defined(__SSE4_2__)
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#define SW_HAS_SSE42
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#include <nmmintrin.h>
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#endif
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#if defined(__SSE4_1__)
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#define SW_HAS_SSE41
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#include <smmintrin.h>
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#endif
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#if defined(__SSSE3__)
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#define SW_HAS_SSSE3
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#include <tmmintrin.h>
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#endif
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#if defined(__SSE3__)
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#define SW_HAS_SSE3
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#include <pmmintrin.h>
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#endif
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#if defined(__SSE2__) || (defined(_M_AMD64) || defined(_M_X64)) // SSE2 x64
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#define SW_HAS_SSE2
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#include <emmintrin.h>
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#endif
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#if defined(__SSE__)
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#define SW_HAS_SSE
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#include <xmmintrin.h>
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#endif
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#if defined(__ARM_NEON) || defined(__aarch64__)
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#if defined(__ARM_FEATURE_FMA)
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#define SW_HAS_NEON_FMA
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#else
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#define SW_HAS_NEON
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#if defined(RLSW_USE_SIMD_INTRINSICS)
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// Check for SIMD vector instructions
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// NOTE: Compiler is responsible to enable required flags for host device,
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// supported features are detected at compiler init but varies depending on compiler
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// TODO: This logic must be reviewed to avoid the inclusion of multiple headers
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// and enable the higher level of SIMD available
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#if defined(__FMA__) && defined(__AVX2__)
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#define SW_HAS_FMA_AVX2
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#include <immintrin.h>
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#elif defined(__FMA__) && defined(__AVX__)
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#define SW_HAS_FMA_AVX
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#include <immintrin.h>
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#elif defined(__AVX2__)
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#define SW_HAS_AVX2
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#include <immintrin.h>
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#elif defined(__AVX__)
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#define SW_HAS_AVX
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#include <immintrin.h>
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#endif
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#include <arm_neon.h>
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#endif
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#if defined(__riscv_vector)
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#define SW_HAS_RVV
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#include <riscv_vector.h>
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#endif
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#if defined(__SSE4_2__)
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#define SW_HAS_SSE42
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#include <nmmintrin.h>
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#elif defined(__SSE4_1__)
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#define SW_HAS_SSE41
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#include <smmintrin.h>
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#elif defined(__SSSE3__)
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#define SW_HAS_SSSE3
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#include <tmmintrin.h>
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#elif defined(__SSE3__)
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#define SW_HAS_SSE3
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#include <pmmintrin.h>
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#elif defined(__SSE2__) || (defined(_M_AMD64) || defined(_M_X64)) // SSE2 x64
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#define SW_HAS_SSE2
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#include <emmintrin.h>
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#elif defined(__SSE__)
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#define SW_HAS_SSE
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#include <xmmintrin.h>
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#endif
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#if defined(__ARM_NEON) || defined(__aarch64__)
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#if defined(__ARM_FEATURE_FMA)
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#define SW_HAS_NEON_FMA
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#else
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#define SW_HAS_NEON
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#endif
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#include <arm_neon.h>
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#endif
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#if defined(__riscv_vector)
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// NOTE: Requires compilation flags: -march=rv64gcv -mabi=lp64d
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#define SW_HAS_RVV
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#include <riscv_vector.h>
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#endif
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#endif // RLSW_USE_SIMD_INTRINSICS
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#ifdef __cplusplus
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#define SW_CURLY_INIT(name) name
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@ -749,31 +756,31 @@ SWAPI void swBindTexture(uint32_t id);
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#endif
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#if (SW_DEPTH_BUFFER_BITS == 16)
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#define SW_DEPTH_TYPE uint16_t
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#define SW_DEPTH_IS_PACKED 1
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#define SW_DEPTH_PACK_COMP 1
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#define SW_DEPTH_MAX UINT16_MAX
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#define SW_DEPTH_SCALE (1.0f/UINT16_MAX)
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#define SW_PACK_DEPTH(d) ((SW_DEPTH_TYPE)((d)*SW_DEPTH_MAX))
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#define SW_UNPACK_DEPTH(p) (p)
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#define SW_DEPTH_TYPE uint16_t
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#define SW_DEPTH_IS_PACKED 1
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#define SW_DEPTH_PACK_COMP 1
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#define SW_DEPTH_MAX UINT16_MAX
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#define SW_DEPTH_SCALE (1.0f/UINT16_MAX)
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#define SW_PACK_DEPTH(d) ((SW_DEPTH_TYPE)((d)*SW_DEPTH_MAX))
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#define SW_UNPACK_DEPTH(p) (p)
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#elif (SW_DEPTH_BUFFER_BITS == 24)
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#define SW_DEPTH_TYPE uint8_t
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#define SW_DEPTH_IS_PACKED 0
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#define SW_DEPTH_PACK_COMP 3
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#define SW_DEPTH_MAX 0xFFFFFFU
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#define SW_DEPTH_SCALE (1.0f/0xFFFFFFU)
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#define SW_PACK_DEPTH_0(d) ((uint8_t)(((uint32_t)((d)*SW_DEPTH_MAX)>>16)&0xFFU))
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#define SW_PACK_DEPTH_1(d) ((uint8_t)(((uint32_t)((d)*SW_DEPTH_MAX)>>8)&0xFFU))
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#define SW_PACK_DEPTH_2(d) ((uint8_t)((uint32_t)((d)*SW_DEPTH_MAX)&0xFFU))
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#define SW_UNPACK_DEPTH(p) ((((uint32_t)(p)[0]<<16)|((uint32_t)(p)[1]<<8)|(uint32_t)(p)[2]))
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#define SW_DEPTH_TYPE uint8_t
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#define SW_DEPTH_IS_PACKED 0
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#define SW_DEPTH_PACK_COMP 3
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#define SW_DEPTH_MAX 0xFFFFFFU
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#define SW_DEPTH_SCALE (1.0f/0xFFFFFFU)
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#define SW_PACK_DEPTH_0(d) ((uint8_t)(((uint32_t)((d)*SW_DEPTH_MAX)>>16)&0xFFU))
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#define SW_PACK_DEPTH_1(d) ((uint8_t)(((uint32_t)((d)*SW_DEPTH_MAX)>>8)&0xFFU))
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#define SW_PACK_DEPTH_2(d) ((uint8_t)((uint32_t)((d)*SW_DEPTH_MAX)&0xFFU))
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#define SW_UNPACK_DEPTH(p) ((((uint32_t)(p)[0]<<16)|((uint32_t)(p)[1]<<8)|(uint32_t)(p)[2]))
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#else // 32 bits
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#define SW_DEPTH_TYPE float
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#define SW_DEPTH_IS_PACKED 1
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#define SW_DEPTH_PACK_COMP 1
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#define SW_DEPTH_MAX 1.0f
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#define SW_DEPTH_SCALE 1.0f
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#define SW_PACK_DEPTH(d) ((SW_DEPTH_TYPE)(d))
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#define SW_UNPACK_DEPTH(p) (p)
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#define SW_DEPTH_TYPE float
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#define SW_DEPTH_IS_PACKED 1
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#define SW_DEPTH_PACK_COMP 1
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#define SW_DEPTH_MAX 1.0f
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#define SW_DEPTH_SCALE 1.0f
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#define SW_PACK_DEPTH(d) ((SW_DEPTH_TYPE)(d))
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#define SW_UNPACK_DEPTH(p) (p)
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#endif
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#define SW_STATE_CHECK(flags) (SW_STATE_CHECK_EX(RLSW.stateFlags, (flags)))
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@ -1136,25 +1143,26 @@ static inline void sw_float_to_unorm8_simd(uint8_t dst[4], const float src[4])
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*(uint32_t*)dst = _mm_cvtsi128_si32(clamped);
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#elif defined(SW_HAS_RVV)
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// TODO: Sample code generated by AI, needs testing and review
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size_t vl = vsetvl_e32m1(4); // Load up to 4 floats into a vector register
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vfloat32m1_t vsrc = vle32_v_f32m1(src, vl); // Load float32 values
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// NOTE: RVV 1.0 specs define the use of __riscv_ prefix for instrinsic functions
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size_t vl = __riscv_vsetvl_e32m1(4); // Load up to 4 floats into a vector register
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vfloat32m1_t vsrc = __riscv_vle32_v_f32m1(src, vl); // Load float32 values
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// Clamp to [0.0f, 1.0f]
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vfloat32m1_t vzero = vfmv_v_f_f32m1(0.0f, vl);
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vfloat32m1_t vone = vfmv_v_f_f32m1(1.0f, vl);
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vsrc = vfmin_vv_f32m1(vsrc, vone, vl);
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vsrc = vfmax_vv_f32m1(vsrc, vzero, vl);
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vfloat32m1_t vzero = __riscv_vfmv_v_f_f32m1(0.0f, vl);
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vfloat32m1_t vone = __riscv_vfmv_v_f_f32m1(1.0f, vl);
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vsrc = __riscv_vfmin_vv_f32m1(vsrc, vone, vl);
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vsrc = __riscv_vfmax_vv_f32m1(vsrc, vzero, vl);
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// Multiply by 255.0f and add 0.5f for rounding
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vfloat32m1_t vscaled = vfmul_vf_f32m1(vsrc, 255.0f, vl);
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vscaled = vfadd_vf_f32m1(vscaled, 0.5f, vl);
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vfloat32m1_t vscaled = __riscv_vfmul_vf_f32m1(vsrc, 255.0f, vl);
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vscaled = __riscv_vfadd_vf_f32m1(vscaled, 0.5f, vl);
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// Convert to unsigned integer (truncate toward zero)
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vuint32m1_t vu32 = vfcvt_xu_f_v_u32m1(vscaled, vl);
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vuint32m1_t vu32 = __riscv_vfcvt_xu_f_v_u32m1(vscaled, vl);
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// Narrow from u32 -> u8
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vuint8m1_t vu8 = vnclipu_wx_u8m1(vu32, 0, vl); // Round toward zero
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vse8_v_u8m1(dst, vu8, vl); // Store result
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vuint8m1_t vu8 = __riscv_vnclipu_wx_u8m1(vu32, 0, vl); // Round toward zero
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__riscv_vse8_v_u8m1(dst, vu8, vl); // Store result
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#else
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for (int i = 0; i < 4; i++)
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{
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@ -1190,12 +1198,12 @@ static inline void sw_float_from_unorm8_simd(float dst[4], const uint8_t src[4])
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_mm_storeu_ps(dst, floats);
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#elif defined(SW_HAS_RVV)
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// TODO: Sample code generated by AI, needs testing and review
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size_t vl = vsetvl_e8m1(4); // Set vector length for 8-bit input elements
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vuint8m1_t vsrc_u8 = vle8_v_u8m1(src, vl); // Load 4 unsigned 8-bit integers
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vuint32m1_t vsrc_u32 = vwcvt_xu_u_v_u32m1(vsrc_u8, vl); // Widen to 32-bit unsigned integers
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vfloat32m1_t vsrc_f32 = vfcvt_f_xu_v_f32m1(vsrc_u32, vl); // Convert to float32
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vfloat32m1_t vnorm = vfmul_vf_f32m1(vsrc_f32, SW_INV_255, vl); // Multiply by 1/255.0 to normalize
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vse32_v_f32m1(dst, vnorm, vl); // Store result
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size_t vl = __riscv_vsetvl_e8m1(4); // Set vector length for 8-bit input elements
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vuint8m1_t vsrc_u8 = __riscv_vle8_v_u8m1(src, vl); // Load 4 unsigned 8-bit integers
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vuint32m1_t vsrc_u32 = __riscv_vwcvt_xu_u_v_u32m1(vsrc_u8, vl); // Widen to 32-bit unsigned integers
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vfloat32m1_t vsrc_f32 = __riscv_vfcvt_f_xu_v_f32m1(vsrc_u32, vl); // Convert to float32
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vfloat32m1_t vnorm = __riscv_vfmul_vf_f32m1(vsrc_f32, SW_INV_255, vl); // Multiply by 1/255.0 to normalize
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__riscv_vse32_v_f32m1(dst, vnorm, vl); // Store result
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#else
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dst[0] = (float)src[0]*SW_INV_255;
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dst[1] = (float)src[1]*SW_INV_255;
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